1. Field of the Invention
The present invention relates to a single transistor type magnetic random access memory device and a method of operating and manufacturing the same. More particularly, the present invention relates to a single transistor type magnetic random access memory device for reading current values flowing through channels of a transistor having gates formed of magnetic tunnel junction (MTJ) cells instead of reading resistance values of the MTJ cells and methods of operating and manufacturing the same.
2. Description of the Related Art
A magnetic random access memory (MRAM), which is a nonvolatile memory device, uses a magnetic characteristic of a material to store data. In principle, the MRAM can realize both rapid reading/writing time of a static random access memory (SRAM) and high integration density of a dynamic random access memory (DRAM) and can rewrite data any time.
A conventional MRAM has a rapid rate and a low driving voltage, which are ideal characteristics for a memory device. However, since the conventional MRAM is formed by depositing several thin films, the structure thereof is complicated and the manufacture thereof is difficult. Also, the conventional MRAM uses tunnel current passing through a tunnel barrier to read a writing state. Thus, the life of the tunnel barrier is short and an additional circuit is required to read the tunnel current.
To solve the above-described problems, it is a first feature of an embodiment of the present invention to provide a single transistor type magnetic random access memory device for reading tunnel current values flowing through channels of a transistor having gates formed of magnetic tunnel junction (MTJ) cells instead of reading tunnel current flowing through conventional MTJ cells.
It is a second feature of an embodiment of the present invention to provide a method of operating the single transistor type magnetic random access memory device.
It is a third feature of an embodiment of the present invention to provide a method of manufacturing the single transistor type magnetic random access memory device.
Accordingly, to provide the first feature, there is provided a single transistor type magnetic random access memory device. The single transistor type magnetic random access memory device includes a substrate, first and second doped regions which are spaced apart from each other and are formed by implanting dopants into the semiconductor substrate, a gate dielectric layer formed on a portion of the semiconductor substrate between the first and second doped regions, an MTJ formed on the gate dielectric layer, word lines formed on the MTJ extending in a first direction which is a same direction as the second doped region, bit lines connected to the first doped region in a second direction perpendicular to the first direction, and an insulating layer for covering the gate dielectric layer, the MTJ, and the word lines to insulate the gate dielectric layer, the MTJ, and the word lines from the bit lines, wherein the first and second doped regions, the gate dielectric layer, and the MTJ constitute a single transistor.
It is preferable that the first doped region is disconnected from a first doped region of another transistor.
It is preferable that the word lines and the bit lines are formed of metal.
The single transistor type magnetic random access memory device may further include the metal strapping lines which are parallel to sources that are disposed parallel to the word lines and which are connected to sources in a predetermined number of memory devices.
To achieve the second feature, there is provided a method of operating a single transistor type magnetic random access memory device. The method includes: (a) applying current Ix to bit lines for addressing, applying current Iy to word lines, making magnetized directions of magnetic layers of an MTJ in an anti-parallel direction, forming a resistance R1, and writing data xe2x80x9c1xe2x80x9d at a selected memory cell; (b) applying current Ix to the bit lines for addressing, applying currentxe2x80x94Iy in a direction opposite to the current Iy to the word lines, making the magnetized directions of the magnetic layers of the MTJ in a parallel direction, forming a resistance R0, and writing data xe2x80x9c0xe2x80x9d at a selected memory cell; and (c) applying a voltage Vds to the bit lines, applying a voltage Vin to the word lines, sensing channel current flowing from a drain that is a first doped region to a source that is a second doped region, and reading the data stored at the step (a) or (b).
It is preferable that (c) is performed by detecting the channel current via a sense amplifier connected to the source.
In (c), the channel current may be detected from metal strapping lines which are parallel to sources disposed parallel to the word lines and are connected to sources in a predetermined number of memory devices.
In (c), the channel may use a depletion mode MOSFET that is doped in advance, to precisely distinguish differences in the channel current due to the difference between the resistances R1 and R0.
In (c), a pulse voltage may be applied to the word lines to read changes in the channel current due to a time delay according to the resistances R1 and R0 during formation of the channel.
To provide the third feature, there is provided a method of manufacturing a single transistor type magnetic random access memory device. The method includes: (a) sequentially forming a gate dielectric layer and MTJ forming layers on a substrate; (b) forming a first insulating layer to cover the resultant layers of (a) on the substrate; (c) exposing an upper portion of the MTJ; (d) forming a word line on the exposed portion of the MTJ; (e) forming a second insulating layer on the first insulating layer to cover the word line; (f) forming a source and a drain by implanting dopants into portions of the substrate at both sides of the MTJ and the word line; (h) forming a third insulating layer, on the second insulating layer, which contacts the source and the drain and covers the stacked layers between the source and the drain; and (i) forming a bit line, on the third insulating layer, which contacts the drain.
It is preferable that (a) includes patterning the layers which are stacked.
It is preferable that (d) includes patterning the word line.
It is preferable that (f) includes: (f1) patterning the first and second insulating layers to expose portions of the substrate at both sides of the gate electric layer and the MTJ; and (f2) implanting dopants into the exposed portions of the substrate to form first and second doped regions which are a drain and a source, respectively, and are spaced apart from each other.
It is preferable that (i) includes: (i1) patterning the third insulating layer to expose the drain; and (i2) forming a conductive bit line, on the third insulating layer, which connects to the exposed drain.